Hall of Fame Nominations

The TCFPGA Hall of Fame is an ongoing and sustainable mechanism to recognize the most significant contributions to the field of FPGAs and Reconfigurable Computing

Nominations for the Class of 2024 Now Open!

Basics

  • Eligibility for consideration: papers published at least 10 years ago in any peer-reviewed conference or journal
  • Nominations: accept public nominations through end of August
  • Number: induct up to 6 papers each year (see intent and notes below)
  • Selection: 20-member selection committee casts ballots. Each committee member given 3 votes to cast. Top 6 receiving at least 10 votes are selected.
    (see intent and notes below)
  • Induction: announced early January; induction annually at an F-conference of the honoree’s choosing (F-conferences: FPGA, FCCM, FPL, FPT)

The nominations currently under consideration for the Class of 2024 are detailed below. Full details of the the nomination procedures and rules are available here.


To make a nomination:

  1. Register on this site, confirm your email, and update your profile with your full name, selecting it under ‘Display name publicly as:’.
  2. While logged in, click ‘New’ in the menu bar, and select ‘HoF Nomination’ or click here.
  3. Fill out all the requested details in the format shown (see detail instructions).
  4. After submission, the nomination will be reviewed by the administrators before being displayed on the website.
  5. Look at other nominations and add your comments.

P. Banerjee, M. Sangtani, and S. Sur-Kolay

Floorplanning for Partially Reconfigurable FPGAs

  • Published: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 1, JANUARY 2011, 2011
  • DOI: 10.1109/TCAD.2010.2079390
  • Citations in Google Scholar: 62

Florent de Dinechin and Bogdan Pasca

Designing Custom Arithmetic Data Paths with FloPoCo

  • Published: IEEE Design and Test of Computers, 2011
  • DOI: 10.1109/MDT.2011.44
  • Citations in Google Scholar: 381

Charles Eric LaForest and J. Gregory Steffan

Efficient multi-ported memories for FPGAs

J. Teifel, R. Manohar

An Asynchronous Dataflow FPGA Architecture

  • Published: IEEE Transactions on Computers, 2004
  • DOI: 10.1109/TC.2004.88
  • Citations in Google Scholar: 182

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