Hall of Fame Nominations

The TCFPGA Hall of Fame is an ongoing and sustainable mechanism to recognize the most significant contributions to the field of FPGAs and Reconfigurable Computing

Nominations for the Class of 2018 Now Open!


  • Eligibility for consideration: papers published at least 10 years ago in any peer-reviewed conference or journal
  • Nominations: accept public nominations through end of August (first year: 1 week after FPL)
  • Number: induct up to 6 papers each year (see intent and notes below)
  • Selection: 20-member selection committee casts ballots. Each committee member given 3 votes to cast. Top 6 receiving at least 10 votes are selected.
    (see intent and notes below)
  • Induction: announced early January; induction annually at an F-conference of the honoree’s choosing (F-conferences: FPGA, FCCM, FPL, FPT)

The nominations currently under consideration for the Class of 2018 are detailed below. Full details of the the nomination procedures and rules are available here.

To make a nomination:

  1. Register on this site, confirm your email, and update your profile with your full name, selecting it under ‘Display name publicly as:’.
  2. While logged in, click ‘New’ in the menu bar, and select ‘HoF Nomination’ or click here.
  3. Fill out all the requested details in the format shown (see detail instructions).
  4. After submission, the nomination will be reviewed by the administrators before being displayed on the website.
  5. Look at other nominations and add your comments.

J. Teifel, R. Manohar

An Asynchronous Dataflow FPGA Architecture

  • Published: IEEE Transactions on Computers, 2004
  • DOI: 10.1109/TC.2004.88
  • Citations in Google Scholar: 156

W.S. Carter, K. Duong, R.H. Freeman, H.-C. Hsieh, J.Y. Ja, J.E. Mahoney, L.T. Ngo, S.L. Sze

A User Programmable Reconfigurable Logic Array

  • Published: IEEE Custom Integrated Circuits Conference, 1986
  • DOI:
  • Citations in Google Scholar: 208

R. Razdan and M. D. Smith

A high-performance microarchitecture with hardware-programmable functional units

  • Published: International Symposium on Microarchitecture (MICRO), 1994
  • DOI: 10.1145/192724.192749
  • Citations in Google Scholar: 492

P. Belanovic and M. Leeser

A library of parameterized floating-point modules and their use

Maya Gokhale, William Holmes, Andrew Kopser, Sara Lucas, Ronald Minnich, Douglas Sweely and Daniel Lopresti

Building and Using a Highly Parallel Programmable Logic Array

J. Varghese and M. Butts and J. Batcheller

An Efficient Logic Emulation System

  • Published: IEEE Transactions on VLSI Systems, 1993
  • DOI: 10.1109/92.238418
  • Citations in Google Scholar: 124

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