Hall of Fame Nominations

The TCFPGA Hall of Fame is an ongoing and sustainable mechanism to recognize the most significant contributions to the field of FPGAs and Reconfigurable Computing

Nominations for the Class of 2023 Now Open!

Basics

  • Eligibility for consideration: papers published at least 10 years ago in any peer-reviewed conference or journal
  • Nominations: accept public nominations through end of August
  • Number: induct up to 6 papers each year (see intent and notes below)
  • Selection: 20-member selection committee casts ballots. Each committee member given 3 votes to cast. Top 6 receiving at least 10 votes are selected.
    (see intent and notes below)
  • Induction: announced early January; induction annually at an F-conference of the honoree’s choosing (F-conferences: FPGA, FCCM, FPL, FPT)

The nominations currently under consideration for the Class of 2023 are detailed below. Full details of the the nomination procedures and rules are available here.


To make a nomination:

  1. Register on this site, confirm your email, and update your profile with your full name, selecting it under ‘Display name publicly as:’.
  2. While logged in, click ‘New’ in the menu bar, and select ‘HoF Nomination’ or click here.
  3. Fill out all the requested details in the format shown (see detail instructions).
  4. After submission, the nomination will be reviewed by the administrators before being displayed on the website.
  5. Look at other nominations and add your comments.

J Bispo, I Sourdis, JMP Cardoso, S Vassiliadis

Regular expression matching for reconfigurable packet inspection

  • Published: IEEE International Conference on Field Programmable Technology (FPT), 2006
  • DOI: 10.1109/FPT.2006.270302
  • Citations in Google Scholar: 231

Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-Mei W. Hwu

FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs

S. Casselman

Virtual Computing and the Virtual Computer

Mike Hutton, Jay Schleicher, David Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault , Andy Lee, Henry Kim and Rahul Saini

Improving FPGA Performance and Area Using an Adaptive Logic Module

Hayden Kwok-Hay So and Robert Brodersen

A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH

Pavle Belanović, Miriam Leeser

A library of parameterized floating-point modules and their use

  • Published: International Conference on Field Programmable Logic and Applications, 2002
  • DOI: 10.1007/3-540-46117-5_68
  • Citations in Google Scholar: 165

Charles Eric LaForest and J. Gregory Steffan

Efficient multi-ported memories for FPGAs

John Villasenor, Chris Jones, and Brian Schoner

Video communications using rapidly reconfigurable hardware

  • Published: IEEE Transactions on Circuits and Systems for Video Technology, 1995
  • DOI: 10.1109/76.475899
  • Citations in Google Scholar: 89

Jason Cong and Zhiru Zhang

An efficient and versatile scheduling algorithm based on SDC formulation

One thought on “An efficient and versatile scheduling algorithm based on SDC formulation

  1. The SDC algorithm was also used in Intel OpenCL Compiler [1] and open-source HLS tools such as LegUp [2] and Bambu [3].

    [1] Czajkowski, Tomasz S., et al. “From OpenCL to high-performance hardware on FPGAs.” 22nd international conference on field programmable logic and applications (FPL). IEEE, 2012.

    [2] Canis, Andrew, et al. “From software to accelerators with LegUp high-level synthesis.” 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES). IEEE, 2013.

    [3] Lattuada, Marco, and Fabrizio Ferrandi. “A design flow engine for the support of customized dynamic high level synthesis flows.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 12.4 (2019): 1-26.

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