Hall of Fame Nominations

The TCFPGA Hall of Fame is an ongoing and sustainable mechanism to recognize the most significant contributions to the field of FPGAs and Reconfigurable Computing

Nominations for the Class of 2019 Now Open!


  • Eligibility for consideration: papers published at least 10 years ago in any peer-reviewed conference or journal
  • Nominations: accept public nominations through end of August (first year: 1 week after FPL)
  • Number: induct up to 6 papers each year (see intent and notes below)
  • Selection: 20-member selection committee casts ballots. Each committee member given 3 votes to cast. Top 6 receiving at least 10 votes are selected.
    (see intent and notes below)
  • Induction: announced early January; induction annually at an F-conference of the honoree’s choosing (F-conferences: FPGA, FCCM, FPL, FPT)

The nominations currently under consideration for the Class of 2019 are detailed below. Full details of the the nomination procedures and rules are available here.

To make a nomination:

  1. Register on this site, confirm your email, and update your profile with your full name, selecting it under ‘Display name publicly as:’.
  2. While logged in, click ‘New’ in the menu bar, and select ‘HoF Nomination’ or click here.
  3. Fill out all the requested details in the format shown (see detail instructions).
  4. After submission, the nomination will be reviewed by the administrators before being displayed on the website.
  5. Look at other nominations and add your comments.

Pete Sedcole, Peter Cheung

Within-die delay variability in 90nm FPGAs and beyond

Andre DeHon

The density advantage of configurable computing

  • Published: IEEE Computer, 2000
  • DOI: 10.1102.839320
  • Citations in Google Scholar: 556

Adrian Ludwin, Vaughn Betz, and Ketan Padalia

High-quality, deterministic parallel placement for FPGAs on commodity hardware

Dev C. Chen and Jan M. Rabaey

A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths

  • Published: IEEE Journal of Solid-State Circuits, 1992
  • DOI: 10.1109/4.173120
  • Citations in Google Scholar: 149

Peter M. Athanas and Harvey F. Silverman

Processor reconfiguration through instruction-set metamorphosis

  • Published: IEEE Computer Magazine, 1993
  • DOI: 10.1109/2.204677
  • Citations in Google Scholar: 519

R. Razdan and M. D. Smith

A high-performance microarchitecture with hardware-programmable functional units

  • Published: International Symposium on Microarchitecture (MICRO), 1994
  • DOI: 10.1145/192724.192749
  • Citations in Google Scholar: 501

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