Floorplanning for Partially Reconfigurable FPGAs

Nominated by: Susmita Sur-Kolay

This paper is one of the first to address the problem of floorplanning in partially reconfigurable heterogeneous FPGAs. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules, reconfiguration overhead can be reduced by fixing the position and shapes of modules common across all instances. We propose a global floorplan generation method PartialHeteroFP to obtain same positions for the common modules across all instances such that the heterogeneous resource requirements of all modules in each instance are satisfied, and the total half-perimeter wirelength over all instances is minimal. Experimental results establish that the proposed PartialHeteroFP produces floorplans very fast, with 100% match of common modules and thereby minimizing the partial reconfiguration overhead.

This employs deterministic graph-theoretic algorithms such as recursive balance bipartitioning to obtain a partition tree with static (common to the sub-task instances) modules assigned judiciously, followed by optimal sizing of the dynamic modules being reconfigured to get floorplan topologies, and finally realizing the topologies on the FPGA fabric.

This is a well-cited paper and industries have been showing keen interest in integrating this fast method since it was published. To the best of our knowledge, most of the papers on partial reconfigurability till date are on design and related issues but only a handful address the floorplaning problem. Hence this paper is worthy of being included in the TCFPGA Hall of Fame.