An Asynchronous Dataflow FPGA Architecture

J. Teifel, R. Manohar
  • Published: IEEE Transactions on Computers, 2004
  • DOI: 10.1109/TC.2004.88
  • Citations in Google Scholar: 182

Nominated by: phwl

Describes an architecture and implementation of an asynchronous FPGA, this having advantages of easy pipelining, energy and robustness compared with traditional designs. Their prototype achieved peak inter-logic block operating frequencies of approximately 400MHz in 0.25um technology, and the work was a precursor to Achronix.

Leave a Comment