Building and Using a Highly Parallel Programmable Logic Array

Maya Gokhale, William Holmes, Andrew Kopser, Sara Lucas, Ronald Minnich, Douglas Sweely and Daniel Lopresti

Nominated by: Andre DeHon

SPLASH was one of the pioneering, FPGA-based reconfigurable computers that
concretely demonstrated the performance/cost advantage of customized FPGA
computing engines for specialized tasks. This article describes how SPLASH
can perform DNA sequence edit-distance computation two orders of magnitude
faster than the supercomputers that were its contemporaries (Cray-2,
Connection Machine 2, Multiflow Trace).

SPLASH was programmed as a linear systolic array. This illustrates how to
effectively harness the computing capacity of FPGAs by exploiting heavy
pipeline parallelism---a technique that remains important today. It also
provided one high-level pattern, the systolic array, for organizing FPGA
computations. The implementation also showed how the datapath widths can
be tailored to the problem, exploiting the bit-level configurability of
FPGA---since the main datapath could be 2b and 4b wide, this allowed the
design to pack more active processing elements onto each FPGA chip than
would be possible if the logic forced the use of larger word sizes.

This paper is highly readable for a broad-audience and brought the lessons
from early reconfigurable computing to the attention of the wider IEEE
computing community.

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