A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths

Dev C. Chen and Jan M. Rabaey
  • Published: IEEE Journal of Solid-State Circuits, 1992
  • DOI: 10.1109/4.173120
  • Citations in Google Scholar: 149

Nominated by: Andre DeHon (editor)

PADDI was perhaps the first Coarse-Grain Reconfigurable Architecture (CGRA) long before the CGRA term was coined. Targeted to provide high-throughput reconfigurable DSP computations, PADDI was an array of 16b arithmetic units, each controlled by a shallow (8 instruction) instruction store operated in VLIW fashion. The paper describes a complete VLSI implementation along with high-level synthesis support.

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