Andre DeHon (editor)

Two members of the Class of 2018 were inducted on February 26, 2018 at the International Symposium on Field-Programmable Gate Arrays.

• A User Programmable Reconfigurable Logic Array.
  William S. Carter, Khue Duong, Ross H. Freeman, Hung-Cheng Hsieh, Jason Y. Ja, John E. Mahoney, Luan T. Ngo, Shelly L. Sze. Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 233–235, 1986. [endorsement]

• An Efficient Logic Emulation System.
  Joseph Varghese, Michael Butts, and Jon Batcheller. IEEE Transactions on VLSI Systems, vol. 1, no. 2, pp. 171–174, June 1993. [endorsement]

A third member of the class was inducted at the IEEE Symposium on Field-Programmable Custom Computing Machines on April 30, 2018.

• Building and Using a Highly Parallel Programmable Logic Array. Maya Gokhale, William Holmes, Andrew Kopser, Sara Lucas, Ronald Minnich, Douglas Sweely and Daniel Lopresti. IEEE Computer, vol. 24, no. 1, pp. 81–89, Jan. 1991. [endorsement]

We will honor the final two Class of 2017 inductee into the FPGA and Reconfigurable Computing Hall of fame on April 30th at the Retrospective Panel at the International Symposium on Field Programmable Custom Computing Machines.

• Programmable Active Memories: Reconfigurable Systems Come of Age. Jean E. Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, Hervé Touati, and Philippe Boucard. IEEE Transactions on Very Large Scale Integration Systems, vol. 4, no. 1, pp. 56–69, March 1996. [endorsement]
• A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology. James R. Heath, Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams. Science, 12 Jun 1998, vol. 280, no. 5370, pp. 1716-1721. [endorsement]

The Retrospective Panel includes talks from Mark Shand and Stan Williams on these classic works.

We recognized the first Class of 2017 inductee into the FPGA and Reconfigurable Computing Hall of fame on February 23rd at the evening banquet at the International Symposium on Field Programmable Gate Arrays.

• FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. Jason Cong and Yuzheng Ding. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 1, pp. 1-12, Jan 1994. [endorsement]